`timescale 1ns / 1ps

module prbs_detector (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        enable,
    input  wire        prbs_in,
    input  wire [7:0]  expected_seed,
    output wire        sync_found,
    output wire        error_detected,
    output wire [15:0] error_count,
    output wire [7:0]  detector_state
);

    // 状态定义
    parameter [1:0] ST_SEARCH = 2'b00;
    parameter [1:0] ST_VERIFY = 2'b01;
    parameter [1:0] ST_LOCKED = 2'b10;
    
    // 本地LFSR寄存器
    reg [7:0] local_lfsr_reg;
    
    // 状态寄存器
    reg [1:0]  sync_state;
    reg [7:0]  match_counter;
    reg [7:0]  verify_counter;
    reg [15:0] error_counter;
    reg [15:0] total_counter;
    reg        sync_found_reg;
    reg        error_flag_reg;
    
    // 本地LFSR反馈
    wire local_feedback;
    assign local_feedback = local_lfsr_reg[7] ^ local_lfsr_reg[5] ^ local_lfsr_reg[4] ^ 
                           local_lfsr_reg[3] ^ local_lfsr_reg[0];
    
    // 期望位和匹配检测
    wire expected_bit;
    wire bit_match;
    assign expected_bit = local_lfsr_reg[7];
    assign bit_match = (prbs_in == expected_bit);
    
    // 本地LFSR更新
    always @(posedge clk or negedge rst_n) 
    begin
        if (!rst_n) 
        begin
            local_lfsr_reg <= (expected_seed == 8'h00) ? 8'h01 : expected_seed;
        end 
        else if (enable) 
        begin
            local_lfsr_reg <= {local_lfsr_reg[6:0], local_feedback};
        end
    end
    
    // 同步检测状态机
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sync_state      <= ST_SEARCH;
            match_counter   <= 8'h00;
            verify_counter  <= 8'h00;
            error_counter   <= 16'h0000;
            total_counter   <= 16'h0000;
            sync_found_reg  <= 1'b0;
            error_flag_reg  <= 1'b0;
        end else if (enable) begin
            case (sync_state)
                ST_SEARCH: 
                begin
                    if (bit_match) 
                    begin
                        match_counter <= match_counter + 1'b1;
                        if (match_counter == 8'd7) 
                        begin
                            sync_state <= ST_VERIFY;
                            verify_counter <= 8'h00;
                            error_counter <= 16'h0000;
                        end
                    end 
                    else 
                    begin
                        match_counter <= 8'h00;
                    end
                end
                
                ST_VERIFY: 
                begin
                    verify_counter <= verify_counter + 1'b1;
                    if (!bit_match) 
                    begin
                        error_counter <= error_counter + 1'b1;
                    end
                    
                    if (verify_counter == 8'd15) 
                    begin
                        if (error_counter <= 16'd1) 
                        begin
                            sync_state <= ST_LOCKED;
                            sync_found_reg <= 1'b1;
                            error_counter <= 16'h0000;
                            total_counter <= 16'h0000;
                        end 
                        else 
                        begin
                            sync_state <= ST_SEARCH;
                            match_counter <= 8'h00;
                            error_counter <= 16'h0000;
                        end
                    end
                end
                
                ST_LOCKED: 
                begin
                    total_counter <= total_counter + 1'b1;
                    if (!bit_match) 
                    begin
                        error_counter <= error_counter + 1'b1;
                        error_flag_reg <= 1'b1;
                    end
                    
                    // 检查错误率（每256位检查一次）
                    if (total_counter[7:0] == 8'hFF) begin
                        if (error_counter > 16'd10) begin
                            // 错误率过高，重新搜索
                            sync_state <= ST_SEARCH;
                            sync_found_reg <= 1'b0;
                            error_flag_reg <= 1'b0;
                            match_counter <= 8'h00;
                            error_counter <= 16'h0000;
                            total_counter <= 16'h0000;
                        end else begin
                            // 重置计数器
                            error_counter <= 16'h0000;
                            total_counter <= 16'h0000;
                        end
                    end
                end
                
                default: begin
                    sync_state <= ST_SEARCH;
                end
            endcase
        end
    end
    
    // 输出连接
    assign sync_found = sync_found_reg;
    assign error_detected = error_flag_reg;
    assign error_count = error_counter;
    assign detector_state = local_lfsr_reg;
    
endmodule